Author: Vincent Diepeveen
Date: 14:34:35 12/19/99
Go up one level in this thread
On December 18, 1999 at 09:21:45, Robert Hyatt wrote:
>On December 18, 1999 at 06:29:22, Tom Kerrigan wrote:
>
>>On December 17, 1999 at 21:50:32, Vincent Diepeveen wrote:
>><cut useless, uninformed tirade about DB's eval function>
>>>Apart from this discussion great discussion about FPGA. You're however
>>>comparing with deep blue. I'm only interested in how much faster my program
>>>can get if i for example put my evaluation to FPGA.
>>
>>I think that putting your eval() on a good FPGA wouldn't be too hard. The main
>>problem is that every time you want to run eval(), you have to send the FPGA the
>>board position and grab the result. So that's a bottleneck. I think you could
>>probably get a net speedup, but it's not like your eval() will run infinitely
>>fast.
>>
>>-Tom
>
>
>Or you can design something like the 1978 Belle hardware. Build a module that
>stores the chess board, generates moves, makes/unmakes moves, and evaluates
>positions. Now you can use the new circuit module to hold the chess board,
>have it update the board (faster than a software make/unmake), and now the
>board position is sitting right by the FPGA eval.
This sounds very smart to do if there is no big overhead in sending
a messege. In fact you now only need to send it 2 integers, so 8 bytes
at maximum (can be compressed easily to 3 bytes if that's a lot quicker.
byte 1: type of message (unmoving, making move, init board #n,
asking for eval)
byte 2: (from)
byte 3: (to)
This needs to be send however *every* move including quiescencesearch
instead of only every full evaluation. So for DIEP we talk here at a
PII450 already about 12k-14k nodes a second here. If this gets
faster because of fpga then we need to send it a lot faster again.
>Problem is it won't be hugely faster, but it will certainly be significantly
>faster. Now, instead of alpha/beta being 15-20% of the total search, it will
>become 90%+
For a 10 fold increase in speed i would directly start making eval in FPGA...
...would give me 3 ply more at *any* hardware as long as you plug in
an AGP card for each processor.
Vincent
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