Author: Robert Hyatt
Date: 12:10:32 01/21/00
Go up one level in this thread
On January 21, 2000 at 14:39:18, Tom Kerrigan wrote: >On January 21, 2000 at 14:03:58, Eugene Nalimov wrote: > >>In his IEEE Micro article Hsu estimated his evaluation function as an equivalent >>to ~40,000 general purpose CPU instructions. (Or is the entire procesing of one >>node? In any case, that doesn't matter - all other work can be done in 0.5-2k >>instructions). > >So let's say you have a nice new Pentium III running at 800MHz. If one >instruction takes one clock cycle, that translates to 20000 NPS. > >If each instruction takes 2 clock cycles (an absolute worst-case scenario) >that's still 10000 NPS. > >If you have the world's best evaluation function, I think 10000 NPS should be >enough for a competitive program. And if it isn't, well, the DB program is >already parallel... > >I don't see why FHH doesn't do this. > >-Tom After creating "cray blitz" I found it difficult to think about trying to write a program for a Micro. And it took a lot of time/effort to do so. After building DB, it would take Hsu a lot of time/effort to try to write a program for a Cray, and then more time/effort to think about a PC-based program. I doubt he is interested in building a firecracker after he has already built a hydrogen bomb...
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