Author: Tom Kerrigan
Date: 16:06:25 06/03/98
Go up one level in this thread
>sure you can... but it doesn't work. It is "an old idea that didn't >work then and doesn't work now".. and when you look at it under a Not true... It's been used successfully in a number of supercomputers. The idea has been around and worked for 20+ years now. In fact, back when RISC was coming to light, there was a fairly large-scale RISC vs. VLIW controversy. >magnifying glass, it is simply a restricted form of superscalar, as was Yes, it's quite clearly superscalar, and sort of "restricted," but at the same time, it simplifies chip design extrordinarily, leaving die space for more execution units, more cache, whatever. >execution in a typical program... and VLIW fails in those just like the >normal super-scalar designs.. except that for most programs, the P6 type VLIW only fails when the compiler fails. Being a software guy yourself, you certainly realize how easy it is to simulate a P6-style "instruction pool" in the compiler compared to building it in hardware. >which, when you think about it, is how everything since the first 586 >has >sort of worked... Not really. The P5 and P6 were built to discover existing parallelism. Merced will expect this information to be generated by the compiler. It really is a fundamental shift of design... Cheers, Tom
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