Author: Robert Hyatt
Date: 16:52:54 06/03/98
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On June 03, 1998 at 19:06:25, Tom Kerrigan wrote: >>sure you can... but it doesn't work. It is "an old idea that didn't >>work then and doesn't work now".. and when you look at it under a > >Not true... It's been used successfully in a number of supercomputers. >The idea has been around and worked for 20+ years now. In fact, back >when RISC was coming to light, there was a fairly large-scale RISC vs. >VLIW controversy. > none that I know of. IE not in Cray, CDC, Hitachi, Fujitsu, texas instruments, etc... ergo I know of *no* successful VLIW computers by anyone. just prototypes here and there... >>magnifying glass, it is simply a restricted form of superscalar, as was > >Yes, it's quite clearly superscalar, and sort of "restricted," but at >the same time, it simplifies chip design extrordinarily, leaving die >space for more execution units, more cache, whatever. no argument there... but it puts the difficult work off onto the compiler, since it has to be done somewhere. And doing this affects binary compatibility in horrible ways... much nicer to have a family of processors that can fetch 1,2,3,4,...,N instructions at a time and execute them, where you set N by how much money you are willing to spend.. > >>execution in a typical program... and VLIW fails in those just like the >>normal super-scalar designs.. except that for most programs, the P6 type > >VLIW only fails when the compiler fails. Being a software guy yourself, >you certainly realize how easy it is to simulate a P6-style "instruction >pool" in the compiler compared to building it in hardware. yes, but i also realize that each rendition of the compiler will go with a specific implementation of the VLIW architecture. And every new enhancement to the hardware by making the instruction longer (as in N-way superscalar where N gets bigger each year) will toss last year's compiler, and executables, and operating systems, and utilities, and .. right out the window... > >>which, when you think about it, is how everything since the first 586 >>has >>sort of worked... > >Not really. The P5 and P6 were built to discover existing parallelism. >Merced will expect this information to be generated by the compiler. It >really is a fundamental shift of design... > >Cheers, >Tom if that turns out to be the internal Merced design, it is probably going to be doomed. Because there are plenty of superscalar architectures that are already faster than Merced will be, and they provide binary compatibility across the entire family of processors...
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