Author: Keith Evans
Date: 10:01:07 04/03/02
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On April 03, 2002 at 03:52:25, Tom Kerrigan wrote: >Also, what kind of FPGA are you planning to use, that you're going to implement >an entire eval function? I ask because I believe it would be impossible to fit a >single set (6) of piece-square tables on the largest Virtex, not to mention >actual logic, although I do notice that the Virtex-II Pro has 22592 slices >(!!!). I also bet it costs more than my life's savings... > >-Tom Correct me if I'm wrong but I don't think that the piece square tables will be a problem. Let's take a pretty middle of the road part such as the XCV1000E - it's a basic Virtex FPGA without extended memory. There are 96 Block SelectRAMs in this part. You can configure them in different ways - I think that the most appropriate way for piece square tables is as 512x8. This is more than enough to hold 64*6 = 384 entries. And that's using 1 RAM - 95 are still available. Since we can do incremental updates of the piece square computation I would think that this would be sufficient. You can use multiple Block SelectRAMs or the dual port nature of the Block SelectRAMs - to increase the effective bandwidth to the RAMs or to store larger values if this is necessary. I can't see any reason why incremental updates could not be used. For normal moves we just need to read a few values to do the update. You just snoop the move bus from the move generator to figure out what to do. If new positions are loaded as would be done in Deep Blue then the baseline piece square computation can be done during the load, and incremental computations used after that. Since you've written a number of chess programs you may see some other barrier of which I am blissfully unaware. Regards, Keith
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