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Subject: Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading

Author: Matt Taylor

Date: 18:45:25 12/13/02

Go up one level in this thread

<snip>
>There are no dual PIV's at the moment.  Only dual xeons.  Xeons are _not_
>PIV's....  For several reasons that can be found on the Intel web site.  That's
>why
>xeons are considered to be their "server class chips" while the PIV is their
>"desktop
>class chip".

Actually the high-clocked Xeons are Pentium 4 Xeons. If memory serves correctly,
the original Xeon was a Pentium 2 with extra cache. The Xeon is just Intel's
name for the SMP version of the chip. It's still the same chip, but in most
cases they add extra cache and enable SMP.

-Matt

• Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Robert Hyatt 19:47:56 12/13/02
  • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Matt Taylor 22:09:50 12/13/02
    • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Robert Hyatt 10:20:39 12/14/02
      • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Matt Taylor 21:53:29 12/14/02
        • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Robert Hyatt 06:24:16 12/15/02
          • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Matt Taylor 20:29:06 12/15/02
            • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Robert Hyatt 20:52:21 12/15/02
              • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Matt Taylor 21:04:45 12/15/02
                • Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading Robert Hyatt 07:14:45 12/16/02

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