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Subject: Re: DIEP NUMA SMP at P4 3.06Ghz with Hyperthreading

Author: Robert Hyatt

Date: 19:47:56 12/13/02

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On December 13, 2002 at 21:45:25, Matt Taylor wrote:

><snip>
>>There are no dual PIV's at the moment.  Only dual xeons.  Xeons are _not_
>>PIV's....  For several reasons that can be found on the Intel web site.  That's
>>why
>>xeons are considered to be their "server class chips" while the PIV is their
>>"desktop
>>class chip".
>
>Actually the high-clocked Xeons are Pentium 4 Xeons. If memory serves correctly,
>the original Xeon was a Pentium 2 with extra cache. The Xeon is just Intel's
>name for the SMP version of the chip. It's still the same chip, but in most
>cases they add extra cache and enable SMP.
>
>-Matt


They are not quite PIVs.  If you use intel's compiler and compile for a PIV
and run it on a PIV the thing runs fine.  If you compile for a PIV and run it
on a xeon it will blow up.

---from experience last week...  :)



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