Author: Jeremiah Penery
Date: 17:41:32 04/13/03
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On April 13, 2003 at 08:14:54, Vincent Diepeveen wrote: >On April 13, 2003 at 08:02:34, Vincent Diepeveen wrote: > >Hello Tom, > >For the endusers there is only 1 way to easily say what SMT is. That is that the >P4 processor can split itself into 2 processors and that they get that second >processor for free and it speeds DIEP up about 15% in nodes a second. > >It may be clear that this is not how i see SMT. I assume SMT is that intel has >put 2 processors near each other which share resources. Using those resources >probably is what takes care they cannot run both at full speed. Your way of seeing SMT is wrong. Everything is exactly the same as a single-processor P4 except that the RAT (Register Allocation Table) and a couple other things are duplicated when using SMT. Execution Resources, Caches (including Trace Cache), Registers[1], and almost everything else are shared in some way. [1] Each logical CPU can use the 8 normal x86 registers. The P4 has some 128 integer and 128 FP physical (rename) registers, which are split up in halves when using SMT. Each logical CPU has access to half of the physical registers. For a very excellent article on SMT, go to Ars-Technica. Here is a link: http://arstechnica.com/paedia/h/hyperthreading/hyperthreading-1.html >In future hopefully less and less resources get shared, until only L2 cache gets >shared where also reads can be done simultaneously, but only a write will be >blocking other cpu from reading/writing to the L2. Then HT will give a major >boost in speed. It is questionable whether we must call it HT then however. I >guess intel will keep using that word for the coming 10 years though. That would be much more like the IBM Power4 design, which is more of a CMP thing than an SMT thing.
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