Author: Bo Persson
Date: 13:32:24 01/22/01
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On January 22, 2001 at 16:12:41, Vincent Diepeveen wrote: >On January 22, 2001 at 09:52:01, Robert Hyatt wrote: > >>On January 22, 2001 at 03:10:18, Gregor Overney wrote: >> [...] >> >> >>why would you conclude that more instructions per cycle slows the cycle >>down? Because the Intel does it? Different animals. Pentium = 64 bit >>bus. Alpha=256. With much higher memory bandwidth to boot.. Exactly, the Alpha instruction set was also designed for this. Intel PIII/PII/Pentium got theirs from the 486/386, which was an extension of the 286, which was an extension of the 8086, which... And then you add MMX, SSE, etc. A total mess! Surprising that Intel can get *any* performance out of this. :-) >The more instructions a clock you do the bigger the problem is >when you have a lot of branches in the program as currently processors >need to reload all the instructions. > >I guess gregor is referring to >that where on the PIII/PII it can execute 3 instructions a clock >you have a 10 penalty for each misprediction > >With P4 which can issue 4 on paper (in reality it has problems >which should prevent it from executing 4 simple integer instructions >a clock) but already has a branch misprediction penalty of 20 clocks >which is hell of a lot. But... The 20 stage pipeline is run on a double clocked ALU, so 20 internal clocks is again 10 external clocks! It also has a trace cache for decoded instructions, so the pipeline doesn't have to do *all* the work again. Bo Persson bop@malmo.mail.telia.com
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