Author: Vincent Diepeveen
Date: 04:18:07 05/12/02
Go up one level in this thread
On May 11, 2002 at 13:14:02, Jeremiah Penery wrote: >On May 11, 2002 at 09:38:15, Vincent Diepeveen wrote: > >>On May 10, 2002 at 22:06:04, Jeremiah Penery wrote: >> >>>On May 10, 2002 at 15:46:11, Vincent Diepeveen wrote: >>> >>>>I gotta see that hammer on my desk first, be able to feel it and touch >>>>it and then run it and see it is faster, before i believe they have >>>>made a 64 bits processor kicking the other 64 bits processors like McKinley >>>>or a cheap K7 0.13 >>> >>>I suppose you've been able to 'feel and touch and run and see it is faster' for >>>a McKinley? No, I didn't think so. If you've read up on it, you might guess >>>that it probably will not be very good for things like chess programs - its >>>strength is in Floating-Point. As far as Hammer beating a 'cheap K7 0.13', what >> >>AMD is developing a new space shuttle. Intel already had one. >>Intel wanted to let it run at 1.2Ghz and above. Now it starts at >>1 Ghz, NOT at 1.2Ghz. IA64 had numerous problems and a long >>development cyclus. >> >>You don't need to be hardware expert to read the specs of the Hammer >>and know that AMD is going to have major problems to meet that. >> >>And only when the design team managed to produce something, >>then we know whether it is going to be a fast CPU. >> >>Also they need a hell of a compiler. > >The compiler can be practically the same as the 32-bit compilers we use now >(MSVC/Intel/GCC/whatever). The only major differences in 64-bit mode are the >allocation of registers (Hammer has twice as many GPRs in 64-bit mode as in >32-bit mode), a few changed/invalid opcodes, address size, and prefixes for >various opcodes. There are other differences, but nothing so serious. > >>That's a lot of conditions before it is fast. More realistic is >>to expect that after it is released, that only the cpu after it >>they will have learned a lot and it will be fast. >> >>Whether a mckinley is going to kick ass i do not officially >>know obviously, but on paper it's awesome and it's not a first >>generation cpu like the hammer is. >> >>So with regard to 32 bits, the hammer isn't going to have major >>problems, but with regard to 64 bits i doubt a lot. >> >>Now let's suppose they make a fast 32 bits cpu with some >>64 bits extensions that work. How fast is the 64 bits then? >> >>Obviously very slow. > >IMO, there's no reason to assume this. > >>Whatever they do, in order to get *any* program use the 64 >>bits parts, they need a special compiler for it. > >Yes, of course. But it's not going to take a huge effort for, say, Microsoft to >make MSVC compile for x86-64. A million times easier than writing a compiler >for the Itanium, at least. > >>It's so many 'if then else' problems that it's even for a major >>company like AMD not going to be easy to be fast soon. >> >>If we look to the K7 MP cpu then i would swear to you as a layman >>here that it is for chess so fast because of the L1 and L2 cache >>strategies (and how they behave parallel). >> >>A huge and fast and very good L1 cache. An outstanding L2 >>cache which over the >>chipset can get data without asking the main memory first. > >The Hammer will have the same cache, just more of it. > >>Let's not focus upon the technical terms. >> >>For a 64 bits cpu to be interesting for chess they need to do something >>no one ever has managed before. > >And that is...? The Alpha seems pretty nice, as well as POWER4, according to >SPECInt numbers (for Crafty). Just because they aren't good for DIEP doesn't >mean they can't be good for chess. You don't even use 64-bit variables in DIEP >(right?), so why would you expect a 64-bit chip to be any faster for you? i'm using 'int' so if a compiler rewrites that to 64 bits, then it's DIEP is a 64 bits program. a 64 bits cpu is completely different from 32 bits. it's not an 'extension'. Because 'extensions' are hell slower. The compiler is not such a trivial thing. If you get 256 registers instead of EAX,EBX,EXC and another few others (with another 44 extra registers to use for register renaming etc) then the importance of the compiler is major. All the speedup has to come out of the compiler, *not* out of different programmed software of course. DIEP was very slow on the first alpha's, which is very irrelevant for the blazing fast plans that are on the board for Hammer and McKinley. On paper diep should be very fast on McKinley and Hammer. In reality however both chips are not comparable. McKinley is 2 generations newer design than Hammer is. Suppose all AMD does is extend their FPU/MMX thing with some extra instructions. Then you have like 8 general MMX registers. That's not worth the effort of course. They need to make 128+ at least easily accessible 64 bits registers at least to make the chip interesting. Then they STILL are a generation behind on the McKinley. With so many registers the importance of the compiler gets overwhelming. It's more than a factor 2 a good compiler on such a chip. There are more issues. How big is the size of this chip going to get? Now the most important question: how high can they clock such a chip? The current plans on paper are simply not realistic.
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