Author: Robert Hyatt
Date: 19:29:38 06/24/02
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On June 24, 2002 at 13:31:20, Bo Persson wrote: >On June 24, 2002 at 10:30:26, Robert Henry Durrett wrote: > >>This addresses half the problem. What if the microprocessor wishes to WRITE >>something. Why not write it directly to a huge cache and bypass RAM entirely? > >It does, sort of. > >The processor writes to the cache, which will update the RAM *eventually*. The >processor doesn't have to wait for the update, so if you're lucky you will not >see the delay. > >Current processors even have write-buffers queueing data going to the cache... Most use "write back" or "copy back" which means that memory is not updated until the modified cache line gets replaced by something else. At that point, the modified (dirty) line is first flushed back to memory before it is replaced by something new. With luck, this turns a bunch of memory write operations into a bunch of cache writes with one memory write later on... And then there is "victim cache" to hold stuff that was "displaced" for a bit (from cache) in case it is needed again soon. > >>If you had extremely large caches, couldn't RAM be dispensed with entirely? > >Or, if you had fast enough RAM, caches could be dispensed of. :-) Micron used to do this. They used to have the fastest 386/486 boxes running. Their entire memory was SRAM rather than DRAM with an SRAM cache. Made them very fast. And much more expensive. Of course, 1 gig of SRAM would be very big compared to 1 gig of DRAM. >That was actually the case for micros until about 15 years ago, when caches were >introduced alongside the "extremely" fast 486. > >A couple of years before that, 120 ns RAM matched an 8 MHz 286 processor pretty >well. > > > >> >>Bob D.
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