Author: fca
Date: 07:58:17 08/12/98
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On August 12, 1998 at 07:29:11, Robert Hyatt wrote: >my P5/233/mmx clocks in at about 70% of the speed of my >P6/200 machine. As I've said before, the P6/PII core logic is simply better >with the instruction pool and speculative execution and register renaming and >you-name-it. Sure, all of us agree here. But to view cache speed (especially) and size differences as having an additive (i.e. multiplicative!) effect together with core speed differences is IMO misleading. If you have something that executes instructions twice as fast, you need a cache that works twice as fast, simply to keep pace (i.e. to prevent a bottleneck). For lower frequency (as % of CPU time) activity like hash accessing, L2 cache speed/size is therefore not so important. Which was my point to Tom, whom I believe(d) was attributing to L2 hit differences part of the reasons for the 2.5x reported by blass uri between a P200MMX and a P2/300 running Junior. I assume L2 only gets stressed by hash activity. >But hashing has little to do with how a program performs on either, due to the >relative infrequency of hash probes compared to all the other stuff like >move generation and positional evaluation... and which activities do not stress L2 cache, but live within L1. :-) SUMMARISED VIEW OF FCA: As long as L2 size/speed keep up with "core MHz ratios times allowance for P-->P2 ", it is not relevant when trying to explain differences in performance of (say) Junior on a P200MMX and a P2/300. Q1. Tom, are you disagreeing with me in any of this? Q2. Bob, ditto? :-) Kind regards fca SUMMARISED VIEW OF FCA: As long as L2 size/speed keep up with "core MHz ratios times allowance for P-->P2 ", it is not relevant when trying to explain differences in performance of (say) Junior on a P200MMX and a P2/300.
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