Author: Matt Taylor
Date: 08:13:03 02/28/03
Go up one level in this thread
On February 28, 2003 at 08:59:08, Vincent Diepeveen wrote: >On February 27, 2003 at 15:35:34, Russell Reagan wrote: > <snip> >I am bad however in reading gcc generated assembly (it looks SO VERY UGLY, >similar to the new PGN format of chessbase) and it seems to me it is >possible that this code can be further optimized. I see no need to put the >board pointer in eax each time. It's using just 2 registers versus very old >MSVC is already using 3. > >Means that at the Opteron and Itanium2 and such processors with more than 8 >GPRs, the GCC compiler will suck major ass of course. It doesn't even know how >to use more than 2 registers! > >But in this example it is doing things *branchless*. > >So i can't actually wait for a visual c++ edition to use CMOV* instructions >and using profile info to optimize branches. > >So in 1 small example we see both the strength of the new generations of >processors released after 1996 (pentiumpro/klamath and newer) and the >weakness of the software (visual c++ 6.0 despite pentiumpro released >in 1996 already still with service packs not using P6 instructions) and the >general inefficiency of the GNU world who isn't using "640KB should be enough >RAM", but instead still is using the lemma "2 registers will do". > >Best regards, >Vincent Diepeveen >diep@xs4all.nl Actually using fewer registers is generally regarded as more optimized. I'm sure that on architectures with billions of registers like Itanium GCC will do just fine. I've been waiting for cmov support in VC for almost 4 years. I'm still waiting. I have doubts that they will add it, even in their Athlon64 compiler. Perhaps I am wrong. I hope I am wrong. -Matt
This page took 0.01 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.