Author: Tom Kerrigan
Date: 16:54:27 07/02/03
Go up one level in this thread
On July 02, 2003 at 14:18:47, Robert Hyatt wrote: >On July 01, 2003 at 21:02:21, Tom Kerrigan wrote: > >>On July 01, 2003 at 20:34:08, Robert Hyatt wrote: >> >>>>You, and many other people, seem to be surprised that the Opteron can execute 32 >>>>bit code at "full speed." >>> >>>Not really. What I suggested was that without the 32 bit kludges, it could >>>probably execute 64 bit code _faster_. >> >>What kludges? I can't think of any 32-bit-mode logic that would add more than >>one gate delay, and what are the chances that that gate delay would end up in >>the critical path, i.e., it's in the longest pipeline stage and it can't be done >>in parallel with anything else? Might as well be zero, I figure. > >I can think of "several kludges". > >sign flag. Which bit does it come from? There are currently 4 choices, >depending on byte, word, doubleword, or now quadword. Hard to choose one >of four bits in one gate delay time. If it's already choosing between 3 bits with one gate delay, it can choose between 4 bits with one gate delay. >>How did Alpha do that? Alpha was never a 32 bit ISA. > >It definitely supports 32 bit instructions, as well as all the way down to >bytes. The cray doesn't, as a counter-point. Sure, but the Alpha ISA has always been 64 bit in the sense that it has always had 64 bit registers, 64 bit busses, 64 bit ALUs, etc. In fact, the first Alphas were so purely 64 bit that you couldn't load an 8/16/32 bit word with one instruction. That's why people were often disappointed with its performance... >>My processor did shifts and rotates, BTW, but with a counter, like early RISC >>designs. Shifting arbitrary word sizes wouldn't have been a problem. >> >>What are the other things? > >All the way back to atomic test/set/exchange operations. The counter approach >is perfectly ok, but it introduces yet another delay. However since the PIV >seems to be a bad "shifter" maybe Intel is listening to your idea. :) I'm not saying my shifter was the best ever. I just couldn't fit a barrel shifter on the FPGA I was using. (Nor would I want to try to map one to logic blocks by hand.) Empirically this problem is not insurmountable. If 64 bit shift performance suffered because of 32 bit backwards compatibility, at least one of these chip vendors would have just put two separate shifters on their chips, one for each width. -Tom
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