Author: Roberto Waldteufel
Date: 22:35:04 11/06/98
Go up one level in this thread
On November 07, 1998 at 00:16:24, Robert Hyatt wrote: >On November 06, 1998 at 17:08:38, Tom Kerrigan wrote: > >>Depends on the program. My guess is that many programs will run much faster on >>the o/c Celery because of its faster L1 cache. Many other programs will run much >>slower because of the smaller size of the L1 cache. >> >>As for the hash table, the village idiot can tell you that a 128 MB hash table >>can not fit in 128 k of L1 cache. Hash table size is a total non-issue, unless >>you use a hash table that's really really really small and it DOES fit in L1 >>cache, in which case it's pretty much useless anyway. >> >>-Tom > >A couple of things.. I assume you meant L2 but typed L1? IE the celeron L1 >is the same as the PII L1 size and speed-wise. L2 is another matter, with >the PII having 512K at clock/2, while the celeronA has 128K at clock/1... > >But as far as hash tables go, they don't count for cache... the average program >executes 2,000 instructions (or more) per node, which means only a couple of >those instructions access the hash table, the rest do other things... small >enough that hashing has little to do with cache efficiency...IMO... > Yes, but don't forget that PII has its cache divided equally between code and data usage, so if the other 1998 instructions do not access large amounts of memory, many of the hash addresses may remain in data cache long enough to get used, since the instructions themselves are fetched in blocks from (hopefully!) the code cache, independantly from whatever is goning on with the data cache. Trouble is, I can't think of any way to actually test this, since you can't turn cache on and off at will. Another point about comparing the Celeron and the Pentium is pipelining. I don't know how it works with the Celeron, but on the PII you can effectively process two instructions at once *if* the code is optimised properly, and the degree to which this is done may have a big effect on how fast the same piece of code runs on the two boxes. So I would think that with a program optimised for Pentium, the Celeron might be slower, whereas for another program not optimised for Pentium, Celeron might be faster (I believe that Rebel is much faster on Celeron). In marked contrast to the plain Pentium and Pentium MMX, the PII and PPro can automatically reorder the instructions within a single instruction fetch block to optimise pipelining, making the execution of non-optimised code much faster, but there are still advantages to be had in terms of execution speed with instruction ordering in order to maximise the efficiency of the instruction block fetching process, which is not automatically optimised at run time like the pipelining is. A big plus for PII and Pro machines (not older Pentiums) is the very vast bit scan instructions. I have no idea how well or badly the Celeron compares here, but these instructions are extremely useful for bitboard operations, so in the context of chess programming this is an important issue, although for most other applications it is probably irrelavent. Best wishes, Roberto > > > >> >> >>On November 06, 1998 at 11:58:19, Ren Wu wrote: >> >>>Hi, all >>> >>>Sorry if this is a little offtopic. >>> >>>I was almost ready to get a PII450 system, until i found that everyone seems be >>>able to overclocking Celeron 300A to 450 as well. The huge price difference make >>>me think twice on this. >>> >>>Did anyone here has a Celeron 300A, and o/c to 450? If so, what is the >>>performance difference compare with the real 450? Will be nice if someone can >>>post some data, like crafty's benchmarks, although Norton SI is also good. >>> >>>Celeron300 A only have 128K L2, is this a big disadvantage even o/c to 450, when >>>you have a huge hashtables (say 128 or 256MB)? >>> >>>Thanks, >>> >>>Ren.
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