Author: Sven Reichard
Date: 05:28:48 12/08/03
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On December 07, 2003 at 09:24:35, Gerd Isenberg wrote: >On December 06, 2003 at 18:08:01, Sven Reichard wrote: >> >Hi Sven, > >i made similar experience with Athlon XP and MMX fill algorithms, with four >independent instruction chains, with up to two MMX-instructions per cycle. >Thus a factor of four speedup for pipelined parallel over sequential. > >I'm not quite sure what instruction latency exactly is. I guess it is time to >decode plus time to execute the instruction. I further guess, that the pure >MMX-ALU execute latency is only one cycle or less (there is also a third >store/load unit) and that decode and execute of different instructions is done >simultaneously with direct path instructions, in opposite to vector path >instructions, which exclusively blocks all decode and execution-units. > >Gerd Gerd, there seems to be no clear definition of latency in the documents, although I deduced from context that it is more or less the time an instruction blocks an ALU. Also, the description of the FPU/MMX pipeline still isn't clear to me. In my code I only use Direct Path instructions which can execute in either of the two pipelines (no MUL's or such). Do you have an idea how far instructions should be spread to avoid store/load hazards? Thanks for your comments, Sven.
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