Author: Eugene Nalimov
Date: 17:21:34 06/17/04
Go up one level in this thread
On June 17, 2004 at 19:45:53, Vincent Diepeveen wrote: >Your intel friend disagrees with the older handbooks posted there. > >I guess you worked for the older McKinley which by the way was called back to >factory for having defects (last X bits of it could randomly go wrong in >floating point when processors >= 900Mhz). > >The todays processors are Madisons. ftp://download.intel.com/design/Itanium2/manuals/25111003.pdf Is May 2004 "new enough" for you? And yes, it was modified for Madison -- I verified that. L2 integer load latency is still 5 cycles. L3 load latency is 12 or 14 cycles. But even with *your* latencies it still will be faster than any Opteron's. Thanks, Eugene PS. BTW, do you still insist that Itanium2 does not store instructions in L2? >www.sara.nl for the lecture of Jason Priestly (Intel) about their caches and the >Madison processor. It quotes 17 cycles for L3 and 7 cycles for L2. > >That makes it effectively slower than Opteron of course which soon is in 0.09 >and will hit for a cheap price very high speeds. > >I wonder how you still try to manage to compete with a 16KB cache which can just >hold very few bundles against a 64KB cache of opteron. > >Practical difference is and remains that opteron is 2 times faster than Madison. >One of the reasons is a better L1 & L2 cache. > >Trivially you cannot see the L2 cache of the Itanium as a L2 cache, the L1 cache >is so small, if you bite the cpu the L2 cache dissappears without a trace in a >back tooth. > >So it's the L3 cache which must compete with it. > >Please do a test with an itanium2 without L3 cache, then you *will* know why >this comment gets made. > >Without L3 cache which limits the cpu for sure < 2Ghz in 0.13, it is worse than >a Celeron!
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