Author: Robert Hyatt
Date: 07:40:50 12/21/99
Go up one level in this thread
On December 21, 1999 at 09:35:04, Tom Kerrigan wrote: >Greg, you keep repeating that FPGAs have memory and that this solves the memory >problem. > >This shows that you have not done one single little bit of logic design in your >entire life. And if you did, you probably got an F in it. > >If an FPGA has a bank of RAM, it takes circuitry to read a value from that RAM. >Then it takes more circuitry to write to that RAM. That's wasting space on your >FPGA and it's adding cycles to the algorithm. And the RAM is not infinitely >fast. There will be latency. I am more concerned about a different problem. This ram is single-ported. Yet a good hardware eval will continually be reading bits and pieces out of this memory... how many pawns on this file.. which side has the left-most passed pawn or candidate, which side has the right-most passed pawn or candidate... This means that memory is going to be accessed from many different eval components. And I don't see how to do this efficiently, as it is going to be a serial bottleneck. In a non-FPGA design, you could distribute this memory around so that this isn't a bit handicap, but here it is. And once you read from the memory, you have to gate the data to the eval component that needs it. This has been the reason that I have said that the FPGA approach has some serious problems to overcome in order for it to work. Eval will be hard enough. A full search will be very tough. Maybe doable, but very tough. I don't know that none of these problems are impossible to solve. But I can say that they will be 'interesting' to solve, at the very least. > >So if you're going to use that RAM on the FPGA, you're forcing the FPGA to >behave like a general purpose computer. And once you do that, well, there's just >no point. > >I think it's sad that you're clinging to this silly fact to save your entire >project here. > >-Tom The hard part here is that he is quite open about not knowing a lot about computer chess. That makes the conversation very difficult at first, because it is necessary to explain the problem, _before_ any attempt at a solution can start. Normally this step is skipped as the problem is already understood. And then we have some 'fluff' thrown in with 90% eval numbers that are really 1/2 of that, and so forth. Data that is _critical_ has to be spot-on accurate, not +/-50% > >On December 20, 1999 at 15:48:35, Greg Lindahl wrote: > >>On December 17, 1999 at 18:59:56, Eugene Nalimov wrote: >> >>>Yes, but Bob wrote exactly why memory is the necessity, and you did not explain >>>how you plain to avoid using it. >> >>Bob explained why memory was a necessity if you wanted to exactly replicate Deep >>Blue's chips. He did not consider either (1) FPGA cards with SRAMs, which are >>common, or (2) whether it's best to put as much into the FPGA as Deep Blue does. >> >>That's why I was disappointed with his comments. >> >>> You can waive your hands in the air as long as >>>you wish; but when it comes down to technical details, I'd recommend you to >>>listen to others >> >>I am happy to listen to others. I have been listening to others. I just don't >>think that a discussion about something that I don't think is a good idea anyway >>(due to 2) and that is fairly moot (due to 1) is worthwhile.
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.