Author: Jeremiah Penery
Date: 19:08:26 08/25/02
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On August 25, 2002 at 21:50:48, Robert Hyatt wrote: >On August 25, 2002 at 11:21:31, Dan Andersson wrote: > >>> >>>If you look at my response to Vincent, there are a few issues that need >>>addressing because NUMA introduces a much higher memory latency for >>>processors that are farther away from the actual memory word needed. This >>>has to be addressed to produce reasonable speedups. >>> >>You say much higher. The latency for one CPU is 80 ns. For MP one hop is 115 ns, > > >First, I don't believe _any_ of those numbers from vendors. If they were >true, the vendors would use that _same_ low-latency memory on the uniprocessor >boxes. But they don't. Which says a lot about the "realness" of the numbers. Perhaps you have not read much about the Hammer architecture. The thing that so greatly reduces latency is that it has a memory controller on the processor die, which scales linearly in speed with the processor. The memory itself is the same as on any other box. In all current processor/chipset configurations, the CPU has to send a memory request to the Northbridge of the motherboard, which runs at a low clockspeed. The northbridge has to send the request on to the main memory, which sends it back through the same channel. Hammer eliminates the northbridge setup completely - memory requests go directly from the processor to the memory banks, via a high-speed HyperTransport tunnel. With multiple CPUs, an access goes through HyperTransport to whatever CPU is directly connected to the needed memory first, then proceeds the same way. Even with this extra step, it is AT LEAST as fast as current CPU-Northbridge-Memory setups (it is the same number of steps as that configuration then), because HyperTransport in general has lower latency than most (all?) current communication protocols. <Large snip> >Hopefully we will see some real numbers soon... But a memory controller on >chip speaks to problems with more than one chip... I eagerly await real numbers also. It's possible that the quoted numbers are lower than any real-world figure we may see, but I suspect that memory latency for Hammer systems will be considerably lower than any current setup, at the very least. As for problems with more than one chip, it doesn't look to cause any kind of problems due to the way it's being handled with multiple HyperTransport tunnels. However, like anything else, we can only wait and see what real figures look like.
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