Author: Robert Hyatt
Date: 18:50:48 08/25/02
Go up one level in this thread
On August 25, 2002 at 11:21:31, Dan Andersson wrote: >> >>If you look at my response to Vincent, there are a few issues that need >>addressing because NUMA introduces a much higher memory latency for >>processors that are farther away from the actual memory word needed. This >>has to be addressed to produce reasonable speedups. >> >You say much higher. The latency for one CPU is 80 ns. For MP one hop is 115 ns, First, I don't believe _any_ of those numbers from vendors. If they were true, the vendors would use that _same_ low-latency memory on the uniprocessor boxes. But they don't. Which says a lot about the "realness" of the numbers. >two hops 150 ns and three are less than 190 ns. That doesn't seem like much to >me. Putting more information in a hash return could amortize the cost to almost >nothing it seems. Maybe, but again, until we get to _real_ latency numbers, it is hard to discuss how to work around them... By "real" I mean "how long does it take to randomly access a word in my memory, then a word in a processor's memory that is one hop away, etc. Vendors smooth those numbers by considering the latency for a "block". But I don't always want a "block" of data where I access every byte in it... >> >>There are plenty of NUMA machines around today, notably from SGI, which can >>be used to understand these issues... >> >And we have those and an IBM system of certain chess fame at the university. I wouldn't call the SP a NUMA architecture... nor the Cray T3 machines... Nor several others that depend mainly on message-passing to emulate a slow form of shared memory. > >>BTW memory latency has been constant for 20+ years now. But as the speed of >>the processors goes up, memory becomes relatively slower. So long as we >>use capacitors for bit storage, this is going to continue to remain a big >>issue. >Yep. But I was commenting on the specifics of the Hammer implementation. And the >memory controller is on chip and some of the overhead will be reduced due to the >fact that parts of it will run faster at higher speeds. It won't reduce the >memory specific latency though. And the speedup will be bounded by the memory >subsystem. > As for the cost of the system. I wouldn't know. But this is a comodity level >system. The HyperTransport bus could end up being mass produced on a scale never >seen before. Excepting the PCI bus maybe. > When I look at it it feels like I'm getting another chance of aquiring a >Transputer based computer. > >MvH Dan Andersson Hopefully we will see some real numbers soon... But a memory controller on chip speaks to problems with more than one chip...
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