Author: Dan Andersson
Date: 08:21:31 08/25/02
Go up one level in this thread
> >If you look at my response to Vincent, there are a few issues that need >addressing because NUMA introduces a much higher memory latency for >processors that are farther away from the actual memory word needed. This >has to be addressed to produce reasonable speedups. > You say much higher. The latency for one CPU is 80 ns. For MP one hop is 115 ns, two hops 150 ns and three are less than 190 ns. That doesn't seem like much to me. Putting more information in a hash return could amortize the cost to almost nothing it seems. > >There are plenty of NUMA machines around today, notably from SGI, which can >be used to understand these issues... > And we have those and an IBM system of certain chess fame at the university. >BTW memory latency has been constant for 20+ years now. But as the speed of >the processors goes up, memory becomes relatively slower. So long as we >use capacitors for bit storage, this is going to continue to remain a big >issue. Yep. But I was commenting on the specifics of the Hammer implementation. And the memory controller is on chip and some of the overhead will be reduced due to the fact that parts of it will run faster at higher speeds. It won't reduce the memory specific latency though. And the speedup will be bounded by the memory subsystem. As for the cost of the system. I wouldn't know. But this is a comodity level system. The HyperTransport bus could end up being mass produced on a scale never seen before. Excepting the PCI bus maybe. When I look at it it feels like I'm getting another chance of aquiring a Transputer based computer. MvH Dan Andersson
This page took 0.01 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.