Author: Tim Foden
Date: 01:57:10 09/27/02
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On September 27, 2002 at 04:48:03, Gerd Isenberg wrote: >from: > > AMD x86-64 Architecture > Programmer’s Manual > Volume 4: > 128-Bit Media Instructions > >=============================================================================== >PSLLDQ Packed Shift Left Logical Double Quadword > >Left-shifts the 128-bit (double quadword) value in an XMM register by the >number of bytes specified in an immediate byte value. The low-order bytes that >are emptied by the shift operation are cleared to 0. If the shift value is >greater than 15, the destination XMM register is cleared to all 0s. > >PSRLDQ Packed Shift Right Logical Double Quadword > >Right-shifts the 128-bit (double quadword) value in an XMM register by the >number of bytes specified in an immediate byte value. The high-order bytes that >are emptied by the shift operation are cleared to 0. If the shift value is >greater than 15, the destination XMM register is cleared to all 0s. >=============================================================================== > >Same instructions are already available on Intel's PIV with SSE2. >I'll hope that "is greater than 15" is a typo or erroneous copied from PSLLW. >It should be 127 here. If you read what it says... it shifts by a BYTE at a time, not a BIT at a time. So the maximum shift is by 15 BYTES. :) Cheers, Tim. >Can anybody confirm this for PIV? > >Regards, >Gerd
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