Computer Chess Club Archives




Subject: Re: Matt Taylor's magic de Bruijn Constant

Author: Gerd Isenberg

Date: 12:33:37 07/14/03

Go up one level in this thread

On July 14, 2003 at 10:54:49, Vincent Diepeveen wrote:

>On July 13, 2003 at 17:10:10, Russell Reagan wrote:
>>On July 13, 2003 at 13:17:56, Bas Hamstra wrote:
>>>It is used *extremely* intensive. Therefore I assumed that most of the time the
>>>table sits in cache. But apparently no... Makes you wonder about other simple
>>>lookup's. A lot of 10 cycle penalties, it seems.
>>Hi Bas,
>>Why you say "10 cycles"? I thought memory latency was many more cycles (~75 -
>Random read from memory at dual P4 or dual K7 is like nearly 400 nanoseconds.
>So that's at 2Ghz around 800 cycles.
>Best regards,

Hi Vincent,

puhh... that's about 1/2 microsecond. I remember the days with
2MHz - 8085 or Z80 CPU - can't beleave it. A few questions...

I'm not familar with dual-architectures. Is it a kind of shared memory via
pci-bus? How do you access such ram - are the some alloc like api-functions?
What happens, if one perocessor writes this memory through cache - what about
possible cache copies of this address in the other processor, or in general how
do the severel processor caches syncronise?
I guess each processor has it's own local main-memory.

Do you know the read latencies of single processor P4 or K7 with state of the
art chipsets?

1.) if data is already in 1. level cache
2.) if data is in 2. level cache but not in 1.
3.) in worst case, if data is only in main memory but in no cache

Thanks in advance,

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