Author: h.g.muller
Date: 08:46:47 02/07/06
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On February 07, 2006 at 10:51:24, Robert Hyatt wrote: >Also hardware dependent. On the Crays, we used 8. But on a vector machine it >takes no longer to access a chain of length 8 than it does to access a single >entry, effectively. For example, on a 2ns T90, it took about 50 clocks to read >the first entry, 1 more clock to read the next, etc. So 57 vs 50 to read 8 vs >1. On the PC this is not going to happen of course. Actually, on the PC this is very similar. Except that the 1-clock accesses are not going to last long, only upto the end of the cache line. Usual SDRAM access pattern is as 6-1-1-1 bus clocks (and 2 64-bit words per such clock with DDR), so to read the cache line takes 9 bus clocks. With a 133MHz front-side bus (advertized as 266MHz because of DDR) on a 1.3 GHz CPU each bus clock equals 10 CPU clocks. So the cache-line read takes 90 CPU clocks, although the first item might already be returned after 60 clocks.
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