Author: Robert Hyatt
Date: 20:37:35 01/26/00
Go up one level in this thread
On January 26, 2000 at 19:16:39, Tom Kerrigan wrote: >On January 26, 2000 at 18:51:02, Bruce Moreland wrote: > >>Maybe, since it is a chip, it does more than one thing at once. I do *not* have >>an EE background, but it would seem to me that you could design a chip that >>would do several things at the same time, and it would take a very long time to >>do the same thing serially. >> >>bruce > >Yup, this is the cool thing about chip design. You can basically do everything >in parallel, and that's what the DB chip does. > >However, when you're talking about a "Deep Blue instruction", I take that to >mean "telling the DB chip to do something." > >Look at it this way: if you had to send the chip 40,000 instructions just to get >one single node searched, you might as well just use a Pentium. > >Bob's claim is so absurd that I could go on for hours listing obvious reasons >why it isn't true. > >-Tom What on earth are you talking about? I never said anything about sending DB 40,000 instructions. I said Hsu might be thinking of the number of different "things" he does in the chip... which doesn't necessarily mean that those translate directly to x86 assembly instructions. IE when I (using bitmaps) ask the question "is this pawn passed" I think of that as one operation, because it _is_ using bitmaps. In Cray Blitz, it was _not_ one instruction by a long shot... You have two different expertises trying to talk with a common language. I would not assume that Hsu meant 40K x86 instructions. I would not assume he meant 40K gates. I would not assume he meant 40K "things" on the chip that get done for each node. In short, I wouldn't assume anything, I would ask. I often "guess" but I indicate when I am doing so. I sometimes know, based on something Hsu has told me. I usually also indicate when I am doing that. But don't try to put insane words into my mouth and then say "that is obviously insane as anybody can see" because _I_ didn't say it. I don't think it is easy to speculate on how many GP instructions it would take to emulate a hardware design. First question has to be "which GP architecture"? I have to think carefully before I would try to estimate how many normal GP instructions it would take to do some of the things I did in Cray Blitz using the magic of vector hardware. IE when I computed mobility, each square had a different mobility score... and one instruction was used to extract the right scores from the vector. I'd have to think about how to write that in X86 assembly. And I could easily be off by a factor of 10 if I didn't spend a day or two thinking about it. Hence my speculation that 40K was "just a number that sounded sufficiently large to make the point" and nothing more. A little thought would suggest that 40K is an impossible number without knowing the architecture. 40K on a PC might mean 100K (or more) on a Sparc, for example. There is too much variability. 40K is _just_ a number.
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