Author: Ernst A. Heinz
Date: 11:44:19 06/03/98
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On June 03, 1998 at 13:11:26, Tom Kerrigan wrote: >The P6 needs a significant amount of circuitry to schedule instructions, >and it only has two integer execution units. The logic necessary to >handle only three execution units is insane, and four is probably >impossible. The new Alpha-21264 CPU has 4 IUs + 2 FPUs and does automatic out-of-order execution with simultaneous 6/8-way instruction retiring at speeds of >= 600MHz (presumably >= 1GHz in the not too far future). This is already state-of-the-art in high-speed RISC CPU design. >Compare this to a VLIW design. With VLIW you can scrap all of your >scheduling logic and add execution units until your heart's content. The real problem of VLIW is that you shift ever more burdens of squeezing performance out of the processors into the compilers. This is of course fine if you know how to do it -- but up to now most compiler construction experts doubt this is true for VLIW ... =Ernst=
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