Author: Tom Kerrigan
Date: 10:11:26 06/03/98
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Bob, I think you misunderstand the point of VLIW. The P6 needs a significant amount of circuitry to schedule instructions, and it only has two integer execution units. The logic necessary to handle only three execution units is insane, and four is probably impossible. Compare this to a VLIW design. With VLIW you can scrap all of your scheduling logic and add execution units until your heart's content. Regarding the VLIW clock speed issue, I think clock speed was confused with number of execution units. The clock speed doesn't make a difference with a VLIW processor, but depending on the instruction set, the number of execution units can. With IA64, Intel is basically building a VLIW processor that doesn't take VLIW instructions. Instead, the instruction stream contains data about which instructions can be run in parallel, which have what memory dependancies, etc. Thus, the scheduling logic on the processor dosen't have to be terribly complicated. Cheers, Tom
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