Author: Robert Hyatt
Date: 06:34:13 03/04/00
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On March 04, 2000 at 00:01:35, Tom Kerrigan wrote: >On March 03, 2000 at 22:28:55, Robert Hyatt wrote: > >>I wasn't thinking carefully earlier, but should have suggested that maybe >>TSCP is much smaller and more 'cache-friendly' than a larger program like >>crafty. The AMD processors had historically had a good cache/cpu interface, > >Yes, I know that TSCP runs entirely out of the original Pentium's 16k (?) L1 >cache. > >A much larger program like Crafty uses the L2 cache. The PII's L2 cache has >always been _much_ better than the Pentium's. > >So it makes me wonder... if you made the Pentium's L2 cache as fast as the >PII's, would it achieve parity again? Seems likely to me. > >-Tom It would help... but without register renaming, it becomes difficult to feed two pipes for long sequences of instructions. I think the p6 would still keep a significant edge, but better cache would narrow the gap...
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