Author: Greg Lindahl
Date: 13:23:24 12/20/99
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On December 17, 1999 at 21:12:52, Robert Hyatt wrote: >It certainly is. I specifically said "you are going about it wrong". And "it" >is not the FPGA approach... it is about your not wanting to understand the >serious problems ahead, _first_. So I can't ask who's interested in the problem first? OK, if you say so; I'm proud to do it all wrong if that's the case. BTW, I am very interested in the problems, and I've been learning all about them from some other people, and they have been nice enough to not tell me I am "going about it wrong". >>Incorrect. If the FPGA design doesn't need any memory, then no one needs to >>solve the problem of getting memory in an FPGA. You pointed out a straw man. > >No, _you_ are incorrect. The chess engine _must_ have memory. FPGA boards come with separate SRAM chips. I said: getting memory in an FPGA. > So a pure FPGA design isn't going to work. Even though today's typical FPGA card has SRAM available? Their main market is FFTs. As you know, an FFT requires memory, and the board manufacturers distribute a library implementation that uses the SRAM. >You originally said you >wanted to do the eval in an FPGA design. That is no good. At the very best, >you can speed up a chess engine by a factor of 2-3, assuming that they use 2/3 >of the compute cycles in the eval. This is not true for all chess engines. There are engines other than yours that have a higher % of time in the eval. It's an interesting trade-off. > DB proved that to >make the thing fly, the _entire_ engine. DB proved that you can make a fast engine by putting it all in a chip. DB did not prove that other approaches could not build a fast engine. The DB approach maximized the design cycle length and costs. There might be more than one way to skin a cat. >Good luck, as I'd love to see something hardware-ish. Thanks for your kind words. -- g
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