Author: Vincent Diepeveen
Date: 02:52:51 02/17/04
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On February 17, 2004 at 00:31:56, Keith Evans wrote: >On February 16, 2004 at 11:37:54, Vincent Diepeveen wrote: > >>On February 15, 2004 at 15:14:16, Slater Wold wrote: >> >> >>> The cards, about $500 a piece. >> >>$3000 a card at least. >> >>Hydra gets sponsored by a FPGA company called Xilinx. >> > >When I recently looked at price quotes for an XC2V1000 part which is apparently >what Chrilly uses I see that you can get some speed grades for under $200 now. Chrilly needs development boards in each computer and add to that a chip with a million programmable gates. 60000 gates is really too little ;) >(When the parts first come out the price in US dollars is closer to the part >number ;-) > >I'm not sure what else is on the cards that Chrilly uses, but it should be >possible to get the prices down closer to Slater's number. Maybe in low volume, >you're paying some licensing fees for a PCI core or something. If you go to >Xilinx's online store they have something for $1500 called a multimedia card >which doesn't have PCI but it does have an VC2V2000 on it plus interfaces which >are probably much more expensive than an edge connector, and some memories on it >as well. (It's actually a fun little project board if you're into that sort of >thing and have some $$$ to drop.) >I do agree that if you look for a cheap off-the-shelf PCI board with a Virtex-II >on it today, that it's quite expensive. At least $1500. But they typically have >RAM and various other things on them too. It would be ironic if chess were the >killer app that got the reconfigurable computing people an affordable card. >(They would still need to shell out _major_ bucks for a synthesizer.) $5000 that's without chip & compiler yet. >Anyways if Chrilly isn't using memory for hash tables and he's still in the >XC2V1000 parts, then I would think that he could get it down to $300. > >I wonder if there's an architecture that would allow you to put a bunch of >little programmable engines on a Xilinx Virtex board. Something like Chuck >Moore's 25X (http://www.forthfreak.net/misc/25x.html) but make each little >processor a bit more powerful than the X18 >(http://www.forthfreak.net/misc/x18.html). Maybe 2k words a pop + plus one >master processor could interface to off-chip DRAM for hash tables. Could you Off chip hashtables are too slow. >partition move generation on such a thing and make it work fast enough to be >interesting? And would it be trivial to partition evaluation - one guy does king the problem with such a thing is that 1 node goes from say 10 clocks to say 50 clocks suddenly thanks to all the extra clocks you want to add, unless you want to add sram. That means in short that for this tiny 3 ply search you get quite a bit more efficient but still not even *close* to a software search. Only shared hashtables are interesting to improve move ordering a lot. However they can't use those because the software search is at a cluster. So last 3 plies of software they don't store 'em anyway. Efficient search you get is if those last 6 plies you can use hashtables. Right now it's losing a ply or 3 to start with. >safety, another part of pawn structure,...? The nice thing about this kind of >architecture would be that you wouldn't have to resynthesize it in order to make >changes. > >-Keith
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