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Subject: A Response From Marc Boule

Author: Slater Wold

Date: 10:22:53 04/02/02


Anyone who doesn't know, Marc Boule is a student of McGill University in
Montreal.  He is currently doing a Thesis on an FPGA based move generator for
his chess program, MBChess.  You can download MBChess, and read several
interesting documents from Marc at http://www.macs.ece.mcgill.ca/~mboul/.

MBChess is a very basic chess program.  (I actually beat it myself, me taking
about 2 minutes a move, and it getting 5 seconds per move.  Seems unfair, but I
cannot beat Fritz 7 at this handicapped time control.)  Marc has not profiled
MBChess, but he *guesses* that MBChess is approx. 50% eval and 50% move gen.
His exact words are:  "Unfortunately I haven't profiled MBChess. I thought that
move generation would account for approximately 50% of the time and that
positional evaluation would count for another 50% but I might be wrong." and
"The results are not that good. I must mention that I am no C expert and my
chess program is not that good. The positional evaluation function is really
ugly and pre-historic. Maybee since the pos. eval. is time consuming, the effect
of a faster move gen."

His results thus far, are as follows:

AMD-K62-450MHz 16MB hash, MBChess vs. MBChess+HW, during opening game:
A) with no heuristics, no positional eval., no quiescence, no hash, just
alpha-beta: hardware is 4.5 times faster (270 kNps vs 57 kNps)
B) with positional, hash and quiescence search: hardware is 2.3 times faster
(97 kNps vs 41 kNps)
C) with B)+Killer: hardware is 2 times faster (115 kNps vs 59 kNps)
These results are a bit disapointing. Even though the pure move generator
speed is almost 5 times faster, when using full heuristics, this drops to
about 2 times faster (hw accelerated vs. software only). During end-game,
the hardware seems to improve more (multiply above numbers by approx. 1.5).

The "2M to 10M" statement I made was a error on my part.  It stemed from a
previous conversation, and other things I was taking from his documentation.


So that puts me kind of back to square one.  Marc has found that his FPGA move
generator can, at best, make/uname 10M moves a second.  On my AMD 2x1.6Ghz with
Crafty, I can make/unmake 30M moves a second.  And Keith Evans (who has been an
exceptional help) has proven that due to PCI bus saturation, even 10M moves per
second will not transfer from FPGA --> Engine.  I still have not had the
oppurtunity to profile Crafty, but I would guess that at best I could not speed
it up more than 15%.

Therefore, the only way to truly speedup Crafty, would be to make an FPGA with a
search and an eval.  Which is a *much* harder task than a move generator.


I am going on vacation tomorrow for 2 weeks.  When I get back I will profile
Crafty, and then look into the possibility of porting the heaviest parts into HW
generated via FPGA's.  It is very possible that I will stick with making the
move generator first, and then move on to the harder parts.

Any ideas/thoughts/comments?  And does anyone want to profile Crafty for me
while my computer is broken.  :D


Thanks to *everyone* who gave feedback on this.  I still plan on doing this.  I
just need more help.  ;)


Slate



PS Keith, do you have another e-mail address?  Yahoo wouldn't accept e-mail from
swbell.net because it's an open relay.  :(



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