Author: Robert Hyatt
Date: 14:08:58 03/03/00
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On March 03, 2000 at 09:18:13, Tom Kerrigan wrote: >On March 03, 2000 at 07:59:47, Robert Hyatt wrote: > >>By the end of the year there will be more than just AMD. At least two other >>companies will likely have a product with such an architecture by year's end. > >I'm all for this. > >The press releases I've read (AMD, IBM, Compaq) imply that two top-of-the-line >processors are going to be combined onto one monster die. > >I find this a little annoying. Things like out-of-order execution, branch >prediction, speculative execution, register renaming, etc. all burn silicon real >estate (not to mention make the control logic impossible to understand), and I >don't really see the benefits. > >I mean, the original Pentium didn't do any of this stuff, and it does more per >clock cycle than a P6. > >I would really like to see some benchmarks of a processor with speculative >execution turned on vs. off. > >I can't imagine that out-of-order execution is doing anything useful, >considering the optimizing compilers we have these days... > >-Tom Problem is the compilers don't know what is going on. IE how many "hidden" registers does the architecture have for renaming? Intel (nor anyone else) will make this a 'constant'. And how does the P5 do more per cycle than a P6 when the p6 can do three ops/cycle, while the P5 drags along at a max of 2, and it requires a very good compiler to do two at a time???
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