Author: Tom Kerrigan
Date: 17:05:57 03/03/00
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On March 03, 2000 at 17:08:58, Robert Hyatt wrote: >Problem is the compilers don't know what is going on. IE how many "hidden" >registers does the architecture have for renaming? Intel (nor anyone else) >will make this a 'constant'. But my point is, why have register renaming at all. I can list a dozen good processors that don't do it. I would like to know the exact percentage speedup it gives you. >And how does the P5 do more per cycle than a P6 when the p6 can do three >ops/cycle, while the P5 drags along at a max of 2, and it requires a very >good compiler to do two at a time??? TSCP (1.42) on an original Pentium/200 searches 136 NPS/MHz. On a Pentium II/300, it searches 119 NPS/MHz. So the Pentium appears to be 15% faster, despite its lack of out-of-order execution, branch predition, speculative execution, register renaming, reservation stations, blah blah blah. I assume this is because the P5 has shorter pipes and doesn't have to flush them all the time due to speculative execution gone wrong. (BTW, the K5 has almost everything beat. It searches 173 NPS/MHz, and it doesn't do anything particularly fancy either.) -Tom
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