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Subject: Re: Introducing "No-Moore's Law"

Author: Robert Hyatt

Date: 19:45:31 02/27/03

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>>>
>
>Robert and Jeremiah,
>
>  Thanks for the posts.
>
>  One point I was trying to make was that every reduction in size is done
>with an exponential increase in cost.  We will reach a time when the
>physics of very small devices will not allow for transistor that can be
>turned "on" and "off" at any reasonable cost.  Given that this is related
>to the size of the atom, it does not make much of a difference if the
>material is Silicon, GaAs, InP, or more exotic materials.
>
>  As Robert had mentioned, increasing the number of processors will then
>be the most effective way of increasing NPS.
>
>
>  Of course, this applies to the semiconductors and hardware only.  Software
>improvements, however, will continue exponentially for all time.  :)
>
>Steve
>


If you have time, I want to ask a very precise set of questions, since we keep
going around and around with the non-engineering types here...

Here they are:

(1) When you design a chip for a particular fab process, do you have a pretty
accurate idea of how fast it is going to clock?  To clarify, some think that you
crank out the design, run it down the fab line, and then if it will run at (say)
5 ghz, you will actually clock them at 3ghz to avoid pushing the envelope too
far too fast.  The engineers I have talked with dispute this with a laugh, but
I thought I'd give you a chance at this as well.

(2) when you design a chip for a particular process, do you have a good idea of
how fast it will run, or do you "wing it" and run a few off and test them to
see what they can clock at?  Again the engineers I talk with say that they
know in advance what it should run at and they run it there.

(3)  Is there any science in the process of designing a chip, or is it a bunch
of "trial and error" operations?  IE in Intel's "roadmap" they are discussing
plans for the next 18 months or so, with predicted clock frequencies.  Are they
able to simply take today's chips and "crank 'em up" after a year, or are they
changing the fab, the dies, etc to make the chip faster.

I hope you see where this is going.  I believe, from the engineers that I
know (and that is not a huge number but I know enough) that this is a very
precise deal.  I designed stuff many years ago using TTL and CMOS stuff, and
the "books" were my bible for doing this, telling me _exactly_ what the gate
delays were for each type of chip (ie LS, etc.)

Looking forward to an answer from someone that might carry a little credence
in the group here.  :)




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