Computer Chess Club Archives




Subject: Re: Introducing "No-Moore's Law"

Author: Jeremiah Penery

Date: 22:36:00 02/27/03

Go up one level in this thread

One interesting place to ask these questions might be at
(specifically, post a new message at: ).  There
are people who read/post there from many relevant companies (Intel, AMD, IBM,
etc.) who have huge knowledge of this stuff.  I'm sure you can get excellent
answers there.

On February 27, 2003 at 22:45:31, Robert Hyatt wrote:

>If you have time, I want to ask a very precise set of questions, since we keep
>going around and around with the non-engineering types here...

Somehow, I get the impression that you're just skimming what I write, assuming I
must be saying what you think I'm saying.

>Here they are:
>(1) When you design a chip for a particular fab process, do you have a pretty
>accurate idea of how fast it is going to clock?  To clarify, some think that you
>crank out the design, run it down the fab line, and then if it will run at (say)
>5 ghz, you will actually clock them at 3ghz to avoid pushing the envelope too
>far too fast.  The engineers I have talked with dispute this with a laugh, but
>I thought I'd give you a chance at this as well.

When Intel shrunk the P4 from .18um to .13um, the processor speed first released
in .13um was the same as the top-end part from .18um - 2GHz.  It's laughable to
think that process shrink wouldn't give them quite a bit of frequency headroom
from the very first, even given the immaturity of the process.  Even on a very
mature process, near the end of a core's lifespan, they _have_ to leave some
headroom at the top, or you get processors like the 1.13GHz P3, which was pushed
right to the limit, and suffered for it.

>(2) when you design a chip for a particular process, do you have a good idea of
>how fast it will run, or do you "wing it" and run a few off and test them to
>see what they can clock at?  Again the engineers I talk with say that they
>know in advance what it should run at and they run it there.

There are a ton of variables that can affect the clock speed attainable by a
certain chip design on a certain process.  If you really feel like discussing
specifics, I can do so.  Here, I will only say that there are things beyond the
path timings that can affect attainable clockspeed.  Thermal issues are a big
deal for this.  Even the packaging used can affect clock scaling of a particular

They can calculate all they want, but they still have to test to make sure
something beyond the scope of their calculations doesn't change the results.

>(3)  Is there any science in the process of designing a chip, or is it a bunch
>of "trial and error" operations?  IE in Intel's "roadmap" they are discussing
>plans for the next 18 months or so, with predicted clock frequencies.  Are they
>able to simply take today's chips and "crank 'em up" after a year, or are they
>changing the fab, the dies, etc to make the chip faster.

Of course they tweak the manufacturing process over its lifetime.  Processor
cores are tweaked less often.  I ask again, do you seriously think that when
Intel went from .18um Willamette P4s at 2GHz to .13um Northwood P4s that they
couldn't increase the clockspeed, even given the immaturity of the process?

>I hope you see where this is going.  I believe, from the engineers that I
>know (and that is not a huge number but I know enough) that this is a very
>precise deal.  I designed stuff many years ago using TTL and CMOS stuff, and
>the "books" were my bible for doing this, telling me _exactly_ what the gate
>delays were for each type of chip (ie LS, etc.)

Modern MPU manufacturing is FAR removed from designing small-scale TTL/CMOS
stuff.  There are way more factors involved in clock scaling potential than just
the gate delays, which themselves are determined by several other factors (e.g.,
thickness of the gate oxide layers - thinner layers allow greater clock

>Looking forward to an answer from someone that might carry a little credence
>in the group here.  :)

I'd really like to see this kind of discussion on RWT (the link given at the
top), so please post there about it if you're interested in hearing several
perspectives on it from very knowledgable and experienced people in the field.

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