Author: Tom Kerrigan
Date: 14:46:10 03/18/03
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On March 18, 2003 at 16:37:35, Robert Hyatt wrote: >>>1. no interleaving, which means that the raw memory latency is stuck at >>>120+ns and stays there. Faster bus means nothing without interleaving, >>>if latency is the problem. >> >>Uh, wait a minute, didn't you just write a condescending post to me about how >>increasing bandwidth improves latency? (Which I disagree with...) You can't have >>it both ways. >> >>Faster bus speed improves both latency and bandwidth. How can it not? > >It doesn't affect random latency whatsoever. It does affect the time taken to >load a >cache line. Which does affect latency in a different way. However, >interleaving does >even better as even though it doesn't change latency either, it will load a >cache line even >faster. Are you kidding me? How can FSB speed _not_ affect latency? If you have 133MHz CAS2 memory and a 100MHz FSB, it takes 2*(1/100M)=20ns + your northbridge overhead to do a random access. Increase the bus speed to 133MHz, now the access takes 2*(1/133M)=15ns + northbridge overhead. So it gets 5ns faster. I don't see how it could possibly _not_ get faster. Where is the flaw in my logic? Second, are you sure an entire cache line has to be filled before any of the data can be used? I thought memory timings like 2-1-1-1 meant that the word that was requested took 2 cycles to access whereas the neighboring words then took 1 cycle each to access during the burst transfer. If the requested word is being sent first, you'd think the northbridge and processor would take advantage of that fact. Do you have any information to the contrary? I mean, if that _wasn't_ the case, don't you think memory timings would be given as the total of all the numbers, e.g., 5 instead of 2-1-1-1? I mean, if the 2 isn't significant, why advertise it? -Tom
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