Author: Keith Evans
Date: 16:16:08 07/28/03
Go up one level in this thread
On July 28, 2003 at 16:52:29, Vincent Diepeveen wrote: >On July 28, 2003 at 16:45:33, Keith Evans wrote: > >>On July 28, 2003 at 13:36:09, Vincent Diepeveen wrote: >> >>>Just compare the design of the move generator of Hsu with chrilly. It is a >>>*massive* difference already. >> >>There are other statements that you made that I could discuss, but this one >>caught my eye... >> >>What are you talking about? What's the difference? How do you know? You seem to >>be implying that Chrilly did a better job than Hsu which I don't believe. > >Yes massive better. > >Hsu has written many articles. > >here is a summary of what Chrilly has said in way more words (voice) >when he was staying here for a few days: > > Hsu was one of the first to make a move generator. He didn't write it in > verilog but in the direct logics of the chip. Very incompatible method. > Custom made by hand. It is incredible that he managed to write at such a > low level anyway. However, a bad result from writing at such a low level is > that the scale and size of the logics is so big that he must have > lost oversight. I write in a more compatible language called Verilog and > that is not comparable to C but way closer than the very 'assembly' way > in which Hsu has written his logics at. It means in short that Brutus > move generator therefore is very small. Note that i MUST make it small > because i am commercial and more gates is more money to pay for. In the > first chip i had just 50000 gates in total and that is very very little to > get a chessprogram working in. > From my viewpoint all the things i have seen so far is utmost beginners > level. This is logical, They are hardware designers, not chessprogrammers. > I focus upon the chess programming technical result. They had so much other > problems to deal with from hardware viewpoint that we can not even compare > it in that sense. > >Best regards, >Vincent I only know of a few architectures that have been used for building hardware move generators. 1 - the Hitech style approach which is going to be very large. (Even with the latest and largest FPGAs I don't think that you would get 64 Hitech chips into one FPGA. It needs a ton of registers.) 2 - the Belle style approach which returns moves in an MVV/LVA order and potentially based on centrality - hardly random but not SEE. Despite what Chrilly allegedly said, Hsu built an efficient move generator. You could fit a lot of those on the latest chips at 0.18 micron or below - much more efficient than anything going in an FPGA in terms of silicon area. It would also run quite fast. Hsu suffered through doing a hand layout, but the result was a really small move generator that would probably run insanely fast on today's technology. 3 - some obscure architectures which had basically random move ordering. (You can find references in Ebeling's book.) Now from what you're saying I infer Chrilly came up with his own architecture. Do you have any idea what makes it novel? From what you're saying he's not planning on more than 2-3 plies of search in hardware so maybe he has a really simple move generator that has basically random move ordering? -K
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