Author: Robert Hyatt
Date: 10:44:13 08/25/03
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On August 25, 2003 at 05:25:35, Sune Fischer wrote: >On August 24, 2003 at 21:53:55, Robert Hyatt wrote: > > >>>>That is a reasonable rate for a program that searches 1M nodes per second. I'm >>>>going at 2.4M so make that about once every 400 nanoseconds. :) Suddenly it >>>>begins to add up in a big way. :) >>>> >>> >>>Ehh, if you search 2.4 Mnodes on a dual that's 1.2 nodes on a single (one every >>>800 ns), I'd say not very far from 1M. I assume you will also have _two_ chips >>>to do the copying :) >> >>_no_. You have exactly _one_ bus connecting _both_ processors to memory. >> >>That's a problem... > >What has the bus to do with cache to cache copying? Cache copying is _important_. If I write to a line of cache on processor A, then processor B has to invalidate that line of cache if it has it. That hurts. Also when I write to a line of cache, that displaces what was there _before_ the copy. And eventually that modified line of cache has to also be written back to real memory. IE for copy/make, you generate a _lot_ of memory traffic... And with two processors sharing a single memory bus, the traffic for two is the same as for the traffic for one CPU that is twice as fast. Remember, cache-to-cache is a misnomer. You have to replace something that is already there, and once you write to a cache line, that cache line _will_ be written to memory before it is destroyed. So cache-to-cache in the case of copy/make often turns into memory-to-memory. > >Each thread would copy to it's own stack, which I presume would reside in the >cache on each respective chip. >Otherwise you're right it would be dead slow, but then that would be the same >for all kinds of tables which I certainly hope isn't the case. It's a problem _everywhere_. And with a dual, it gets worse as a copy to a line in one cache invalidates that line in another cache when the content address is the same. That makes duals potentially much worse. > >-S.
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